The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a delay locked loop (DLL) circuit and a DLL control method thereof.
Generally, since a high-speed semiconductor memory device processes data in synchronization with an external clock, it delays the external clock through a DLL circuit to generate an internal clock and controls the data to be outputted in accurate synchronization with the edge of the external clock.
The DLL circuit does not operate in a specific mode, i.e., a power mode or a self refresh mode, and then starts to operate after the end of the specific mode.
However, when a conventional power supply of a semiconductor memory device is unstable, a timing between a clock (hereinafter, referred to as a DLL clock) outputted from a DLL circuit before the start of the specific mode and a DLL clock after the end of the specific mode may be mismatched. Due to the timing mismatch of the DLL clock, failure may occur in the semiconductor memory device.